The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
For example, the need to perform higher resolution lithography processes grows. One lithography technique used to address this need is extreme ultraviolet lithography (EUVL). Masks used in EUVL present new challenges. For example, a multi-layer (ML) structure is used in an EUVL mask, and a microscopic non-flatness (caused by a defect, for example) on a surface of the substrate of the EUVL mask may deform the films deposited subsequently thereon. When an incident light is reflected from a deformed region, also referred to as a phase defect, it may experience a phase difference with respect to a light reflected from a normally formed region. A phase defect may affect print fidelity and result in severe pattern distortion on a wafer substrate. However, conventional mask inspections may not efficiently identify the phase defect, especially when the phase defect is caused by a defect located at a lower portion of the ML structure. Furthermore, conventional wafer defect inspections may identify a huge number of potential defects, and the process to eliminate the nuisance defects while keeping defects of interest (e.g., caused by the phase defect of the EUVL mask) may be difficult, expensive, and time consuming.
Therefore, it is desired to provide an efficient and a feasible method to detect and classify defects.